🔌 E1 Multiplexer Architecture & Functions

Comprehensive Technical Study Guide
Digital Communications Engineering | System Architecture Deep Dive

🏗️ System Architecture Overview

Complete System Block Diagram

LINE INTERFACE
HDB3 Decoder
Clock Recovery
INPUT BUFFER
Elastic Store
Frame Align
FRAME PROCESSOR
FAS Detection
CRC Check
TSI & MEMORY
Time Switch
Control Store
OUTPUT BUFFER
Formatter
HDB3 Encoder
CONTROL PROCESSOR
Microcontroller
Configuration
SYSTEM MEMORY
Data RAM
Program Flash
SIGNALING PROC
TS16 Handler
CAS Extract

📋 Detailed Architectural Notes

1. Hierarchical Architecture Model

The E1 multiplexer follows a three-layer architecture:

  • Physical Layer (Layer 1): Handles electrical characteristics, line coding (HDB3), and clock recovery
  • Frame Layer (Layer 2): Manages frame alignment, error checking, and time slot delineation
  • Application Layer (Layer 3): Controls time slot interchange, signaling extraction, and system configuration

2. Data Flow Architecture

Data moves through the system via three distinct paths:

  • High-Speed Data Path: Serial bit stream at 2.048 Mbps through buffers and TSI (hardware-controlled)
  • Control Path: Processor bus accessing configuration registers and memory (typically 8-16 bit parallel)
  • Signaling Path: Extracted from TS16, processed separately, mapped to channel status registers

3. Clock Distribution Architecture

Multiple clock domains require careful synchronization:

  • Recovered Clock: Extracted from incoming E1 line (2.048 MHz ± 50 ppm)
  • System Clock: Local oscillator or master reference (high stability, ± 4.6 ppm)
  • Frame Clock: 8 kHz derived from system clock (125 μs period)
  • Processor Clock: Typically 10-50 MHz for control operations

🔍 Line Interface Unit (LIU) - Detailed Functions

1.1 HDB3 Decoder Architecture

Function: Converts HDB3 (High Density Bipolar 3) line code to unipolar binary data while maintaining clock information.

Detailed Operation:

  • Input Stage: Differential receiver with 75Ω or 120Ω termination
  • Equalization: Adaptive equalizer compensates for cable attenuation (0-6 dB at 1024 kHz)
  • HDB3 Rules:
    • Bipolar violation (V) replaces four consecutive zeros
    • Bipolar alternation maintained for ones
    • Even parity of pulses since last violation
  • Error Detection: Monitors for bipolar violations (BVI alarm)
HDB3 Decoding Logic:

Input: + 0 0 0 + - 0 0 0 - + 0 0 0 +
Rule Check: Count zeros between pulses
If zeros = 4: Replace with 000V (V = violation, same polarity as previous pulse)
Output: 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1
Clock Recovery: Extracted from pulse transitions (density = 2.048 MHz max)

1.2 Clock Recovery Circuit (CRC)

Phase-Locked Loop (PLL) Architecture:

🔧 PLL Components

  • Phase Detector: Compares input data transitions with VCO output
  • Loop Filter: Low-pass filter (cutoff 100-1000 Hz)
  • VCO: Voltage Controlled Oscillator at 2.048 MHz
  • Divider: Feedback divider (÷1 for direct lock)

📊 Performance Specs

  • Capture Range: ± 100 ppm (± 205 Hz)
  • Lock Time: < 10 ms
  • Jitter Generation: < 0.01 UI (Unit Interval)
  • Jitter Tolerance: Meets ITU-T G.823
Clock Quality Requirements: The recovered clock must meet G.813 specifications for SDH/SONET compatibility. Short-term stability (wander) must be < 18 μs over 1000 seconds.

1.3 Line Monitoring Functions

Alarm Detection Criteria Typical Response Register Bit
LOS (Loss of Signal) No transitions for 10-255 bit periods Switch to protection, AIS generation SR[0] = 1
LOF (Loss of Frame) 2-5 consecutive incorrect FAS Enter hunt mode, buffer reset SR[1] = 1
RAI (Remote Alarm) Bit 3 of TS0 = 1 for 5 frames Report to management system SR[2] = 1
AIS (Alarm Indication) All ones in TS0 for 5 frames Propagate alarm downstream SR[3] = 1
BVI (Bipolar Violation) Two consecutive same-polarity pulses Increment error counter SR[4] = 1

💾 Buffer System - Architecture & Functions

Architecture

Type: Dual-port FIFO (First-In-First-Out)
Size: 2-8 frames (512-2048 bits)
Organization: Circular buffer with read/write pointers

Detailed Functions

  • Clock Domain Crossing: Bridges recovered clock to system clock
  • Jitter Absorption: Filters high-frequency phase variations (> 10 Hz)
  • Frequency Compensation: Accommodates ± 50 ppm frequency offset
  • Slip Control: Manages controlled slips at frame boundaries
Pointer Arithmetic:
Write Ptr: 0 → 1 → 2 → ... → N → 0 (wrap)
Read Ptr: Follows with delay D
Fill Level = (Write - Read) mod N
Thresholds: Low = 25%, High = 75%

Architecture

Type: Double-buffered RAM
Size: 256 bits × 2 banks (Bank A/B)
Access: Ping-pong operation for seamless frame processing

Detailed Functions

  • Frame Alignment: Stores bits until FAS detected
  • Parallel Access: Converts serial to parallel for processing
  • Double Buffering: One bank written while other read
  • Delay Compensation: Fixed 125μs or 250μs delay
Bank Switching: Occurs at frame boundary (every 125μs). Switch signal generated by frame counter = 0.

Architecture

Type: PLL-controlled FIFO
Size: 128-512 bits
Control: Phase comparator adjusts read clock

Detailed Functions

  • Wander Reduction: Filters low-frequency phase drift (< 10 Hz)
  • Clock Smoothing: Output clock stability < 0.01 ppm
  • Holdover: Maintains output during input loss (holdover mode)
  • Phase Build-out: Prevents phase jumps during switchover
ITU-T G.823 Compliance: Jitter buffer ensures output meets 1.5 UIpp (Unit Intervals peak-peak) specification.

📋 Buffer Management Detailed Notes

Slip Control Algorithm

NORMAL
50% ± 25%
→
WARNING
>75% or <25%
→
SLIP
Repeat/Drop
→
RECOVER
Back to 50%

Slip Implementation Details:

  • Slip Direction: Positive (repeat) or Negative (drop)
  • Slip Size: Always 1 frame (256 bits, 125μs)
  • Slip Rate: Maximum 1 per 24 hours (G.822)
  • Audio Impact: 125μs glitch (inaudible) vs 62.5μs click (if bit slip)

Pointer Management in SDH/SONET Context

When E1 is mapped into SDH VC-12:

  • VC-12 Pointer: 10-bit pointer indicating frame offset
  • Pointer Adjustments: ± 1 unit (1 byte = 8 bits) per frame
  • Justification Bytes: C1, C2 bits indicate positive/negative justification
  • E1 Buffer Interaction: SDH pointer adjustments absorbed by E1 elastic buffer

🖥️ Frame Processor - Architecture & Functions

1. Frame Alignment Unit (FAU) - Detailed Architecture ▼

State Machine Architecture

RESET
→
HUNT
Search FAS
→
VERIFY
2 frames
→
SYNC
Monitor

Detailed FAU Functions

  • Hunt State: Bit-by-bit search for FAS pattern (0011011) in TS0
    • Shift register compares incoming bits with FAS pattern
    • Hamming distance calculation (threshold = 0 for exact match)
    • False alignment protection: Verify over 2 consecutive frames
  • Sync State: Monitor FAS every frame
    • Frame counter tracks position within multiframe
    • CRC-4 verification (if enabled)
    • Loss of sync after 2-5 consecutive errors (configurable)
FAS Detection Timing:
Worst case hunt time: 1 frame (256 bits) = 125μs
Average hunt time: 0.5 frame = 62.5μs
Verification time: 2 frames = 250μs
Total alignment time: < 375μs typical
2. CRC-4 Processor - Error Detection Architecture ▼

CRC-4 Implementation

Generator Polynomial: G(x) = x⁴ + x + 1 (ITU-T G.704)

Architecture Components

  • CRC Generator: LFSR (Linear Feedback Shift Register) with 4 stages
  • Smf (Sub-multiframe) Counter: Tracks 2-frame sub-multiframes (Smf I and II)
  • Error Counter: 8-bit register accumulating CRC mismatches
  • ES (Errored Seconds) Counter: 16-bit register for G.821 performance monitoring
CRC-4 Calculation Process:

1. Initialize shift register to 0000
2. Clock all bits of TS0 (except CRC bits 1-4) through LFSR
3. Invert LFSR output (1's complement)
4. Compare with received CRC bits
5. If mismatch: Increment error counter

Coverage: Detects all single and double bit errors in TS0
Undetected Error Probability: 1/16 (6.25%)

Multiframe Structure for CRC-4

Frame TS0 Bits 1-4 TS0 Bits 5-8 Function
0 C1 0 0 1 1 0 1 1 Smf I indicator, FAS
1 0 0 1 1 0 1 1 1 FAS
2 C2 0 0 1 1 0 1 1 Smf II indicator, FAS
3 0 0 1 1 0 1 1 1 FAS
4-15 C1/C2/C3/C4 1 1 1 1 CRC bits, NFAS
3. Time Slot Counter & Timing Generator ▼

Timing Architecture

Bit Clock 2.048 MHz
Bit Counter 0-255 (8-bit)
Time Slot Clock 256 kHz
TS Counter 0-31 (5-bit)
Frame Clock 8 kHz
Frame Counter 0-15 (4-bit)

Counter Chain Implementation

2.048 MHz
BitCnt[7:0]
0x00 → 0xFF
TS Clock
TSCnt[4:0]
0-31
Frame Pulse

Timing Functions

  • Bit Counter: Addresses individual bits within frame (0-255)
  • TS Counter: Selects current time slot (0-31), decoded for channel enable
  • Frame Counter: Tracks multiframe position (0-15) for signaling
  • Strobe Generation: Derived pulses for memory access, latch enable

🧮 Time Slot Interchange (TSI) - Detailed Architecture

TSI Core Architecture

Input Stage

32 × 8-bit Serial-in
Parallel-out Shift Registers

Converts serial TS to parallel
⇄

Data Memory

32 × 8-bit Dual-Port RAM
Double Buffered (2 banks)

Stores one frame of data
↑↓

Control Memory (Connection Memory)

32 × 5-bit RAM | Address = Output TS | Data = Input TS

Written by processor to establish connections
⇄

Output Stage

32 × 1 8-to-1 Multiplexers
Parallel-in Serial-out

Converts parallel to serial TS

TSI Operation Modes

🔄 Straight-Through

TSn (in) → TSn (out)

Control Memory[n] = n
No switching delay
Used for transparent mode

🔀 Cross-Connect

TSi (in) → TSj (out)

Control Memory[j] = i
125μs delay (1 frame)
Any-to-any switching

📢 Broadcast

TSi (in) → Multiple TS (out)

Control Memory[j] = i
Control Memory[k] = i
Conference/announcement

🗑️ Idle

No connection (all zeros)

Control Memory[n] = 0x1F (invalid)
Output = 0x00
Channel not in use

📋 TSI Implementation Details

Sequential vs. Parallel TSI

Architecture Speed Requirement Complexity Application
Sequential (Single RAM) 2 × 2.048 MHz = 4.096 Mbps Low Small systems (1-4 E1)
Parallel (Dual RAM) 2.048 MHz (each RAM) Medium Standard E1 MUX
Space-Switch + TSI (TST) Multiple planes High Large digital switches

Control Memory Access Protocol

The processor updates connection maps via specialized access:

  • Address Bus: 5 bits selecting output time slot (0-31)
  • Data Bus: 5 bits specifying input time slot (0-31)
  • Write Strobe: Updates control memory atomically
  • Read Back: Verification of connection map
  • Shadow Register: Double buffering for hitless updates
Critical Timing: Control memory updates must occur during frame overhead (TS0 or TS16) to prevent data corruption. Some systems use "connection memory B" while "A" is active, then switch.

🗂️ Memory System - Detailed Architecture

🚀 Registers (Flip-Flops) - Control/Status < 10 ns
⚡ SRAM (Static RAM) - TSI Data/Control 10-50 ns
💾 Dual-Port RAM - Frame Buffers 20-100 ns
📀 Flash/EPROM - Program Storage 100 ns - 1 μs
1. Register Map - Detailed Bit Fields ▼

Control Register 0 (CR0) - System Configuration

Bit Name Type Function
7 SYS_RST R/W System reset (1 = reset, auto-clear)
6 LOOPBACK R/W Digital loopback mode
5 CLK_SEL R/W 0 = Recovered clock, 1 = Master clock
4 TSI_EN R/W TSI enable (0 = bypass)
3 CRC_EN R/W CRC-4 processing enable
2 CAS_EN R/W Channel Associated Signaling enable
1-0 RESERVED RES Reserved, write 0

Status Register 0 (SR0) - Real-Time Status

Bit Name Type Function
7 LOS R/O Loss of Signal detected
6 LOF R/O Loss of Frame alignment
5 RAI R/O Remote Alarm Indication
4 AIS R/O Alarm Indication Signal
3 SLIP R/O Slip event occurred (sticky)
2 CRC_ERR R/O CRC error in last multiframe
1 SYNC R/O Frame alignment achieved
0 INT_PEND R/O Interrupt pending
2. Data Memory Organization ▼

Memory Map Structure (Typical 8KB System)

0x0000 - 0x000F: Control Registers (16 bytes)
0x0010 - 0x001F: Status Registers (16 bytes)
0x0020 - 0x003F: TSI Control Memory (32 bytes)
0x0040 - 0x004F: Signaling Memory (16 bytes)
0x0050 - 0x0250: Frame Buffer A (512 bytes)
0x0250 - 0x0450: Frame Buffer B (512 bytes)
0x0450 - 0x0850: Elastic Buffer (1KB)
0x0850 - 0x1FFF: Reserved/Stack (6KB)

Memory Access Arbitration

Multiple masters require arbitration:

  • Frame Processor: Highest priority, deterministic access every 3.9μs
  • Control Processor: Medium priority, burst access during configuration
  • DMA Controller: Low priority, background data moves
Dual-Port RAM Solution: Frame buffers use true dual-port SRAM allowing simultaneous read/write. Control memory uses time-division multiplexing (TDM) access - processor writes during even frames, hardware reads during odd frames.
3. Signaling Memory Architecture ▼

CAS (Channel Associated Signaling) Memory Map

16 bytes store ABCD bits for 30 voice channels:

Multiframe Structure (16 frames):

Frame 0: TS16 = 0 0 0 0 X X X X (MFAS)
Frame 1-15: TS16 = A B C D A B C D (CH1-2, CH3-4, etc.)

Memory Organization:
Byte 0: CH1 (ABCD) + CH16 (ABCD) from Frame 1
Byte 1: CH2 (ABCD) + CH17 (ABCD) from Frame 2
...
Byte 15: CH15 (ABCD) + CH30 (ABCD) from Frame 15

Update Rate: Every 2ms (multiframe period)

Signaling Change Detection

Hardware compares current multiframe with previous:

  • Change Mask: 16-bit register indicating which channels changed
  • Interrupt Generation: Optional IRQ on any signaling change
  • Debounce: 3-multiframe confirmation prevents glitches

⚙️ Control Processor - Architecture & Functions

Processor Subsystem Architecture

CPU Core (8/16-bit Microcontroller)

8051, AVR, or ARM Cortex-M0+ | Clock: 10-50 MHz

Interrupt Controller

  • Frame Interrupt (8 kHz)
  • Alarm Interrupts
  • Timer Interrupts
  • UART Interrupts

Timers/Counters

  • Watchdog Timer
  • Performance Counters
  • Slip Interval Timer
  • Generic Timers (2)

Communication

  • UART (Management)
  • SPI (External Flash)
  • I²C (EEPROM)
  • Parallel Bus (Registers)

Firmware Architecture

1
Initialization Task
Hardware reset, clock configuration, memory test, register initialization. Runs once at startup (~100ms).
2
Frame Interrupt Service Routine (ISR)
Executes every 125μs. Handles real-time processing: slip detection, alarm monitoring, signaling extraction. Must complete within 100μs.
3
Background Task Scheduler
Non-real-time tasks: Performance monitoring (G.821), configuration updates, management interface (CLI/SNMP), LED control.
4
Alarm Handling Task
State machine processing for LOS, LOF, AIS. Implements protection switching, alarm propagation, logging.

📋 Processor Implementation Notes

Real-Time Constraints

Critical Timing: Frame ISR must complete within 100μs (80% of frame period) to allow for interrupt latency and background tasks. Worst-case execution time (WCET) analysis required for certification.
  • Interrupt Latency: < 1μs (12 clock cycles at 12MHz)
  • Context Switch: Hardware stack, 8-level deep
  • Priority Levels: 2 (High: Frame/Alarm, Low: Background)

Memory Protection

Critical for system stability:

  • Write Protection: Control registers protected by key sequence
  • Buffer Guards: Hardware address checking prevents buffer overflow
  • Watchdog: Resets system if ISR misses 3 consecutive frames

📊 Performance Monitoring & Standards Compliance

📈 G.821 Performance Metrics

  • Errored Seconds (ES): Seconds with ≥1 error
  • Severely Errored Seconds (SES): Seconds with BER ≥ 10⁻³
  • Unavailable Seconds (UAS): Consecutive SES ≥ 10 seconds
  • Error Free Seconds (EFS): Seconds with zero errors

⏱️ G.823 Jitter/Wander Specs

  • Jitter (f > 10 Hz): < 1.5 UI peak-peak
  • Wander (f < 10 Hz): < 18 μs (1000s interval)
  • TIE (Time Interval Error): Bounded integration of frequency offset
  • MTIE: Maximum TIE over observation interval

🔔 Alarm Hierarchy

  • Critical: LOS, LOF (service affecting)
  • Major: AIS, RAI (remote defect)
  • Minor: CRC errors, slips (degraded)
  • Info: Performance thresholds

🛡️ Protection Switching

  • 1+1 Protection: Hot standby E1 line
  • Switch Time: < 50 ms (G.841)
  • Revertive: Return to working after repair
  • Non-revertive: Stay on protection
Availability Calculation:

MTBF (Mean Time Between Failures): 50,000 - 100,000 hours typical
MTTR (Mean Time To Repair): 2-4 hours
Availability = MTBF / (MTBF + MTTR) = 99.995% to 99.998%

With 1+1 protection:
Availability = 1 - (1-A)² = 99.9999% (six nines)

🧮 Interactive Design Calculators

Buffer Size Designer

50 ppm
24 hours
1.5 UI
Calculating...

Memory Bandwidth Calculator

1.2x
Calculating...

📋 Summary & Study Checklist

🔑 Key Architectural Concepts

  • Three-layer architecture (Physical/Frame/Application)
  • Clock domain crossing via elastic buffers
  • Frame alignment state machine (Hunt→Verify→Sync)
  • TSI space-time-space switching
  • Dual-port memory for concurrent access
  • Signaling multiframe (16 frames, 2ms)

⚠️ Critical Design Considerations

  • Buffer size vs. slip rate trade-off
  • Memory bandwidth bottleneck analysis
  • Interrupt latency in frame processing
  • Clock stability and holdover performance
  • Alarm detection hysteresis
  • Protection switching time constraints

🎓 Comprehensive Study Checklist

Standards Mastery: Ensure thorough understanding of ITU-T G.703 (physical), G.704 (frame), G.706 (CRC), G.732 (primary multiplex), G.823 (jitter), and G.821 (performance) specifications.

© 2026 Digital Communications Engineering | E1 Multiplexer Architecture Study Guide

Comprehensive coverage of ITU-T G.703, G.704, G.706, G.732, G.823, and G.821 standards